1. Field of the Invention
The present invention relates to a semiconductor device and a timing adjusting method for the semiconductor device, in particular, to a semiconductor device which automatically adjusts internal timing and a timing adjusting method for the semiconductor device.
2. Description of Related Art
It has been known that an internal timing signal (hereinafter, referred to as merely a “timing signal”) is used to control an operation of each of circuit sections of a semiconductor device. For example, the timing signal is generated from an external clock signal by a delay circuit. In a semiconductor device, recently, lowering a power supply voltage has advanced for demand for reduction of a power consumption amount. As the lowering of the power supply voltage, dependency of delay time of a transistor (tpd) on variation of the power supply voltage VDD and a threshold voltage Vth is increasing. For this reason, variation of delay time in the delay circuit may increase. Due to such increase of the variation in the delay circuit, it may be difficult to ensure an internal operation margin in the semiconductor device.
As a method of suppressing a variation of the delay time in the delay circuit, it could be considered to integrate a resistance element into the delay circuit as a delay element. Thereby, influence of variations of the power supply voltage VDD and the threshold voltage Vth in a transistor of the delay circuit can be suppressed. As a result, the variation of delay time in the delay circuit can be suppressed. For example, it is described in “Delay Circuit, Semiconductor Storage Device and Method for controlling Semiconductor Storage Device” described in Japanese Patent Publication No. 3,866,594, to use a resistance element in a delay circuit.
In conjunction with the above description, Japanese Patent Application Publication (JP-A-Heisei 10-294379 (corresponding to U.S. Pat. No. 5,796,993) discloses “Method and Apparatus for Optimization of Semiconductor Device by Using On-chip Confirmation Circuit”. This method optimizes timing of a semiconductor integrated circuit device. The method including (a) receiving a control delay amount; (b) producing a modified device timing based on the control delay amount; (c) testing the modified device timing by using on-chip confirmation circuit to determine if the semiconductor integrated circuit device can function as a device; (d) receiving a new control delay amount, where the new control delay amount replaces the control delay amount and is different from the control delay amount; and (e) repeating steps (b) to (e) to determine an optimal control delay amount for the semiconductor integrated circuit device.
Other factors varying the delay time in the delay circuit include manufacturing variation. In a process with a large manufacturing variation of the resistance element, the delay circuit using the resistance element is influenced by the manufacturing variation of the resistance element in addition to manufacturing variation of transistors. For this reason, even if variations of the power supply voltage VDD and the threshold voltage Vth of the transistor can be suppressed, the variation of the delay time in the delay circuit may not be sufficiently reduced due to the influence of manufacturing variation. There is a demand for a technique of suppressing variation including the manufacturing variation in the delay time.